commit 5697207f95e4757b740122c53354855b380057dd
Author: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Date:   Thu Jun 16 13:00:52 2022 +0200

    Linux 4.9.319
    
    Link: https://lore.kernel.org/r/20220614183722.061550591@linuxfoundation.org
    Tested-by: Florian Fainelli <f.fainelli@gmail.com>
    Tested-by: Shuah Khan <skhan@linuxfoundation.org>
    Tested-by: Guenter Roeck <linux@roeck-us.net>
    Tested-by: Linux Kernel Functional Testing <lkft@linaro.org>
    Tested-by: Jon Hunter <jonathanh@nvidia.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 71078b82164e36c893dc0764866e3783b1988fb4
Author: Josh Poimboeuf <jpoimboe@kernel.org>
Date:   Mon May 23 09:11:49 2022 -0700

    x86/speculation/mmio: Print SMT warning
    
    commit 1dc6ff02c8bf77d71b9b5d11cbc9df77cfb28626 upstream
    
    Similar to MDS and TAA, print a warning if SMT is enabled for the MMIO
    Stale Data vulnerability.
    
    Signed-off-by: Josh Poimboeuf <jpoimboe@kernel.org>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit da06c60d1dfef826512068d09aed3b6a70b5e5c9
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:35:15 2022 -0700

    KVM: x86/speculation: Disable Fill buffer clear within guests
    
    commit 027bbb884be006b05d9c577d6401686053aa789e upstream
    
    The enumeration of MD_CLEAR in CPUID(EAX=7,ECX=0).EDX{bit 10} is not an
    accurate indicator on all CPUs of whether the VERW instruction will
    overwrite fill buffers. FB_CLEAR enumeration in
    IA32_ARCH_CAPABILITIES{bit 17} covers the case of CPUs that are not
    vulnerable to MDS/TAA, indicating that microcode does overwrite fill
    buffers.
    
    Guests running in VMM environments may not be aware of all the
    capabilities/vulnerabilities of the host CPU. Specifically, a guest may
    apply MDS/TAA mitigations when a virtual CPU is enumerated as vulnerable
    to MDS/TAA even when the physical CPU is not. On CPUs that enumerate
    FB_CLEAR_CTRL the VMM may set FB_CLEAR_DIS to skip overwriting of fill
    buffers by the VERW instruction. This is done by setting FB_CLEAR_DIS
    during VMENTER and resetting on VMEXIT. For guests that enumerate
    FB_CLEAR (explicitly asking for fill buffer clear capability) the VMM
    will not use FB_CLEAR_DIS.
    
    Irrespective of guest state, host overwrites CPU buffers before VMENTER
    to protect itself from an MMIO capable guest, as part of mitigation for
    MMIO Stale Data vulnerabilities.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    [cascardo: arch/x86/kvm/vmx.c has been split and context adjustment at
     vmx_vcpu_run]
    [cascardo: moved functions so they are after struct vcpu_vmx definition]
    [cascardo: fb_clear is disabled/enabled around __vmx_vcpu_run]
    [cascardo: conflict context fixups]
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit b7efb3a62fffa509e21d076aa2e75331c79fe36d
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:34:14 2022 -0700

    x86/speculation/mmio: Reuse SRBDS mitigation for SBDS
    
    commit a992b8a4682f119ae035a01b40d4d0665c4a2875 upstream
    
    The Shared Buffers Data Sampling (SBDS) variant of Processor MMIO Stale
    Data vulnerabilities may expose RDRAND, RDSEED and SGX EGETKEY data.
    Mitigation for this is added by a microcode update.
    
    As some of the implications of SBDS are similar to SRBDS, SRBDS mitigation
    infrastructure can be leveraged by SBDS. Set X86_BUG_SRBDS and use SRBDS
    mitigation.
    
    Mitigation is enabled by default; use srbds=off to opt-out. Mitigation
    status can be checked from below file:
    
      /sys/devices/system/cpu/vulnerabilities/srbds
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    [cascardo: adjust for processor model names]
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 48e40e2cccb37c1f9c345014ca55c41bb8baee66
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:33:13 2022 -0700

    x86/speculation/srbds: Update SRBDS mitigation selection
    
    commit 22cac9c677c95f3ac5c9244f8ca0afdc7c8afb19 upstream
    
    Currently, Linux disables SRBDS mitigation on CPUs not affected by
    MDS and have the TSX feature disabled. On such CPUs, secrets cannot
    be extracted from CPU fill buffers using MDS or TAA. Without SRBDS
    mitigation, Processor MMIO Stale Data vulnerabilities can be used to
    extract RDRAND, RDSEED, and EGETKEY data.
    
    Do not disable SRBDS mitigation by default when CPU is also affected by
    Processor MMIO Stale Data vulnerabilities.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 8acd4bf9427eaf18a801db3f2508a2d89914d51d
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:32:13 2022 -0700

    x86/speculation/mmio: Add sysfs reporting for Processor MMIO Stale Data
    
    commit 8d50cdf8b8341770bc6367bce40c0c1bb0e1d5b3 upstream
    
    Add the sysfs reporting file for Processor MMIO Stale Data
    vulnerability. It exposes the vulnerability and mitigation state similar
    to the existing files for the other hardware vulnerabilities.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 6ecdbc9dc777a5b66a9ec293af88ab330dd644a2
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:31:12 2022 -0700

    x86/speculation/mmio: Enable CPU Fill buffer clearing on idle
    
    commit 99a83db5a605137424e1efe29dc0573d6a5b6316 upstream
    
    When the CPU is affected by Processor MMIO Stale Data vulnerabilities,
    Fill Buffer Stale Data Propagator (FBSDP) can propagate stale data out
    of Fill buffer to uncore buffer when CPU goes idle. Stale data can then
    be exploited with other variants using MMIO operations.
    
    Mitigate it by clearing the Fill buffer before entering idle state.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Co-developed-by: Josh Poimboeuf <jpoimboe@redhat.com>
    Signed-off-by: Josh Poimboeuf <jpoimboe@redhat.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 5da4d16872d3d15dac54b5a6f83f54e28bc3a477
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:30:12 2022 -0700

    x86/bugs: Group MDS, TAA & Processor MMIO Stale Data mitigations
    
    commit e5925fb867290ee924fcf2fe3ca887b792714366 upstream
    
    MDS, TAA and Processor MMIO Stale Data mitigations rely on clearing CPU
    buffers. Moreover, status of these mitigations affects each other.
    During boot, it is important to maintain the order in which these
    mitigations are selected. This is especially true for
    md_clear_update_mitigation() that needs to be called after MDS, TAA and
    Processor MMIO Stale Data mitigation selection is done.
    
    Introduce md_clear_select_mitigation(), and select all these mitigations
    from there. This reflects relationships between these mitigations and
    ensures proper ordering.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit a11f2f05f5c605d1f6573b0cdcd2a6f38667fda1
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:29:11 2022 -0700

    x86/speculation/mmio: Add mitigation for Processor MMIO Stale Data
    
    commit 8cb861e9e3c9a55099ad3d08e1a3b653d29c33ca upstream
    
    Processor MMIO Stale Data is a class of vulnerabilities that may
    expose data after an MMIO operation. For details please refer to
    Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst.
    
    These vulnerabilities are broadly categorized as:
    
    Device Register Partial Write (DRPW):
      Some endpoint MMIO registers incorrectly handle writes that are
      smaller than the register size. Instead of aborting the write or only
      copying the correct subset of bytes (for example, 2 bytes for a 2-byte
      write), more bytes than specified by the write transaction may be
      written to the register. On some processors, this may expose stale
      data from the fill buffers of the core that created the write
      transaction.
    
    Shared Buffers Data Sampling (SBDS):
      After propagators may have moved data around the uncore and copied
      stale data into client core fill buffers, processors affected by MFBDS
      can leak data from the fill buffer.
    
    Shared Buffers Data Read (SBDR):
      It is similar to Shared Buffer Data Sampling (SBDS) except that the
      data is directly read into the architectural software-visible state.
    
    An attacker can use these vulnerabilities to extract data from CPU fill
    buffers using MDS and TAA methods. Mitigate it by clearing the CPU fill
    buffers using the VERW instruction before returning to a user or a
    guest.
    
    On CPUs not affected by MDS and TAA, user application cannot sample data
    from CPU fill buffers using MDS or TAA. A guest with MMIO access can
    still use DRPW or SBDR to extract data architecturally. Mitigate it with
    VERW instruction to clear fill buffers before VMENTER for MMIO capable
    guests.
    
    Add a kernel parameter mmio_stale_data={off|full|full,nosmt} to control
    the mitigation.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    [cascardo: arch/x86/kvm/vmx.c has been moved]
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 91ab1073814aa5d44fb3d8e2423ffdc61a421cac
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:28:10 2022 -0700

    x86/speculation: Add a common function for MD_CLEAR mitigation update
    
    commit f52ea6c26953fed339aa4eae717ee5c2133c7ff2 upstream
    
    Processor MMIO Stale Data mitigation uses similar mitigation as MDS and
    TAA. In preparation for adding its mitigation, add a common function to
    update all mitigations that depend on MD_CLEAR.
    
      [ bp: Add a newline in md_clear_update_mitigation() to separate
        statements better. ]
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 19aa53c9eb2cf3a78ee44800e20bb34babe60f45
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:27:08 2022 -0700

    x86/speculation/mmio: Enumerate Processor MMIO Stale Data bug
    
    commit 51802186158c74a0304f51ab963e7c2b3a2b046f upstream
    
    Processor MMIO Stale Data is a class of vulnerabilities that may
    expose data after an MMIO operation. For more details please refer to
    Documentation/admin-guide/hw-vuln/processor_mmio_stale_data.rst
    
    Add the Processor MMIO Stale Data bug enumeration. A microcode update
    adds new bits to the MSR IA32_ARCH_CAPABILITIES, define them.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    [cascardo: adapted family names to the ones in v4.19]
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 63c10e92b86a6cddd5294cda9f80eb7961cb1046
Author: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Date:   Thu May 19 20:26:07 2022 -0700

    Documentation: Add documentation for Processor MMIO Stale Data
    
    commit 4419470191386456e0b8ed4eb06a70b0021798a6 upstream
    
    Add the admin guide for Processor MMIO stale data vulnerabilities.
    
    Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    [cascardo: index.rst conflict fixup]
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit caa0dd5c078267cfa685f06a8986763e1191f232
Author: Gayatri Kammela <gayatri.kammela@intel.com>
Date:   Thu Jan 21 13:50:04 2021 -0800

    x86/cpu: Add another Alder Lake CPU to the Intel family
    
    commit 6e1239c13953f3c2a76e70031f74ddca9ae57cd3 upstream.
    
    Add Alder Lake mobile CPU model number to Intel family.
    
    Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
    Signed-off-by: Tony Luck <tony.luck@intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Link: https://lkml.kernel.org/r/20210121215004.11618-1-tony.luck@intel.com
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 0180c22721463af7de99c1d3312c2a146bc054a8
Author: Tony Luck <tony.luck@intel.com>
Date:   Mon Jul 20 21:37:49 2020 -0700

    x86/cpu: Add Lakefield, Alder Lake and Rocket Lake models to the to Intel CPU family
    
    commit e00b62f0b06d0ae2b844049f216807617aff0cdb upstream.
    
    Add three new Intel CPU models.
    
    Signed-off-by: Tony Luck <tony.luck@intel.com>
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Link: https://lore.kernel.org/r/20200721043749.31567-1-tony.luck@intel.com
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 64d90b7226dcda3f2adb79b559080c3b0b0cb81d
Author: Kan Liang <kan.liang@linux.intel.com>
Date:   Tue Oct 8 08:50:02 2019 -0700

    x86/cpu: Add Comet Lake to the Intel CPU models header
    
    commit 8d7c6ac3b2371eb1cbc9925a88f4d10efff374de upstream.
    
    Comet Lake is the new 10th Gen Intel processor. Add two new CPU model
    numbers to the Intel family list.
    
    The CPU model numbers are not published in the SDM yet but they come
    from an authoritative internal source.
    
     [ bp: Touch up commit message. ]
    
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Reviewed-by: Tony Luck <tony.luck@intel.com>
    Cc: ak@linux.intel.com
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: Ingo Molnar <mingo@kernel.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: x86-ml <x86@kernel.org>
    Link: https://lkml.kernel.org/r/1570549810-25049-2-git-send-email-kan.liang@linux.intel.com
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 1574d3df3bfa3dc8a226f10df2ffc6b1bc992bdd
Author: Kan Liang <kan.liang@linux.intel.com>
Date:   Mon Jun 3 06:41:20 2019 -0700

    x86/CPU: Add more Icelake model numbers
    
    commit e35faeb64146f2015f2aec14b358ae508e4066db upstream.
    
    Add the CPUID model numbers of Icelake (ICL) desktop and server
    processors to the Intel family list.
    
     [ Qiuxu: Sort the macros by model number. ]
    
    Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
    Cc: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
    Cc: rui.zhang@intel.com
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Tony Luck <tony.luck@intel.com>
    Cc: x86-ml <x86@kernel.org>
    Link: https://lkml.kernel.org/r/20190603134122.13853-1-kan.liang@linux.intel.com
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 26b367f8fdb285973e6e016a4c347eedf68db700
Author: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
Date:   Thu Feb 14 17:27:08 2019 +0530

    x86/CPU: Add Icelake model number
    
    commit 8cd8f0ce0d6aafe661cb3d6781c8b82bc696c04d upstream.
    
    Add the CPUID model number of Icelake (ICL) mobile processors to the
    Intel family list. Icelake U/Y series uses model number 0x7E.
    
    Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Cc: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
    Cc: Dave Hansen <dave.hansen@linux.intel.com>
    Cc: "David E. Box" <david.e.box@intel.com>
    Cc: dvhart@infradead.org
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: Ingo Molnar <mingo@redhat.com>
    Cc: Kan Liang <kan.liang@linux.intel.com>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: platform-driver-x86@vger.kernel.org
    Cc: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
    Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: x86-ml <x86@kernel.org>
    Link: https://lkml.kernel.org/r/20190214115712.19642-2-rajneesh.bhardwaj@linux.intel.com
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit d14cee8b6c2ff42a233921f9c7f2a8bc0025fad9
Author: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
Date:   Fri Feb 2 19:13:35 2018 +0530

    x86/cpu: Add Cannonlake to Intel family
    
    commit 850eb9fba3711e98bafebde26675d9c082c0ff48 upstream.
    
    Add CPUID of Cannonlake (CNL) processors to Intel family list.
    
    Cc: Dave Hansen <dave.hansen@linux.intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    cc: Ingo Molnar <mingo@redhat.com>
    Cc: "H. Peter Anvin" <hpa@zytor.com>
    Cc: x86@kernel.org
    Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
    Suggested-by: Tony Luck <tony.luck@intel.com>
    Signed-off-by: Megha Dey <megha.dey@linux.intel.com>
    Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com>
    Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 761fd846a24a436943502bdb136e397d9ce3bfc9
Author: Zhang Rui <rui.zhang@intel.com>
Date:   Mon Dec 16 16:33:44 2019 +0800

    x86/cpu: Add Jasper Lake to Intel family
    
    commit b2d32af0bff402b4c1fce28311759dd1f6af058a upstream.
    
    Japser Lake is an Atom family processor.
    It uses Tremont cores and is targeted at mobile platforms.
    
    Reviewed-by: Tony Luck <tony.luck@intel.com>
    Signed-off-by: Zhang Rui <rui.zhang@intel.com>
    Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit 3b68328c004ecb920e4be1bec33de74844e4b489
Author: Guenter Roeck <linux@roeck-us.net>
Date:   Wed Jun 17 07:14:10 2020 -0700

    cpu/speculation: Add prototype for cpu_show_srbds()
    
    commit 2accfa69050c2a0d6fc6106f609208b3e9622b26 upstream.
    
    0-day is not happy that there is no prototype for cpu_show_srbds():
    
    drivers/base/cpu.c:565:16: error: no previous prototype for 'cpu_show_srbds'
    
    Fixes: 7e5b3c267d25 ("x86/speculation: Add Special Register Buffer Data Sampling (SRBDS) mitigation")
    Reported-by: kernel test robot <lkp@intel.com>
    Signed-off-by: Guenter Roeck <linux@roeck-us.net>
    Signed-off-by: Borislav Petkov <bp@suse.de>
    Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
    Link: https://lkml.kernel.org/r/20200617141410.93338-1-linux@roeck-us.net
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

commit f397f5c53780ea12fcd4b8648e549370e5105a2a
Author: Gayatri Kammela <gayatri.kammela@intel.com>
Date:   Thu Sep 5 12:30:18 2019 -0700

    x86/cpu: Add Elkhart Lake to Intel family
    
    commit 0f65605a8d744b3a205d0a2cd8f20707e31fc023 upstream.
    
    Add the model number/CPUID of atom based Elkhart Lake to the Intel
    family.
    
    Signed-off-by: Gayatri Kammela <gayatri.kammela@intel.com>
    Signed-off-by: Tony Luck <tony.luck@intel.com>
    Cc: Linus Torvalds <torvalds@linux-foundation.org>
    Cc: Peter Zijlstra <peterz@infradead.org>
    Cc: Rahul Tanwar <rahul.tanwar@linux.intel.com>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Link: https://lkml.kernel.org/r/20190905193020.14707-3-tony.luck@intel.com
    Signed-off-by: Ingo Molnar <mingo@kernel.org>
    Signed-off-by: Thadeu Lima de Souza Cascardo <cascardo@canonical.com>
    Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>